This section is intended to provide a background or context to the embodiments disclosed below. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise explicitly indicated herein, what is described in this section is not prior art to the description in this application and is not admitted to be prior art by inclusion in this section.
Many programs utilize analog multiplexers for common signal processing prior to A/D (analog-to-digital) converters. The A/D converters and time (or time division) multiplexers are often controlled by state machines that require little to no software intervention. A state machine can cycle through inputs and after allowing sufficient settling time will start the A/D conversion process. After the A/D conversion is complete the state machine will select the next multiplexer channel to its conversion and go through all signals.
FIG. 1 shows an example of a conventional control system 10 comprising a time multiplexer (time division multiplexer) 14, an A/D converter 12 and a state machine 16. The multiplexer 14 comprises 4 channels with corresponding 4 input signals 20a, 20b, 20c and 20d. Each channel has a resistor 22 (R) and a switch (24a, 24b, 24c or 24d respectively). The parasitic output capacitance 26 (CCharge) is charged by the input signal 20a, 20b, 20c or 20d when the corresponding switch 24a, 24b, 24c or 24d is open, and then provided to the A/D converter 12 for further processing (analog-to-digital conversion). The timing of opening and closing of switches 24a, 24b, 24c and 24d is controlled by a state machine 16 in a cycle manner and typically each channel may be open for a time period from approximately 10 microseconds to 10 millisecond.